The present invention relates to a semiconductor integrated circuit device and a manufacturing technique therefor; and more particularly, the invention relates to a technique which is effective for application to a DRAM or a semiconductor integrated circuit device, wherein the DRAM and a logic circuit, such as a logical control circuit or an arithmetic logic circuit or the like, are placed on one semiconductor substrate in mixed form.
Memory cells of a DRAM are generally placed at points where a plurality of word lines and a plurality of bit lines intersect on a principal surface of a semiconductor substrate in matrix form. Each memory cell comprises one memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) and one information storage capacitive element (capacitor) electrically connected in series therewith. The memory cell selection MISFET is formed within an active region whose periphery is surrounded by a device separation region, and principally comprises a gate oxide film, a gate electrode constructed integrally with each word line, and a pair of semiconductor regions constituting a source and a drain. Each bit line is placed in an upper portion of the memory cell selection MISFET and is electrically connected to one of the source and drain shared between two adjacent memory cell selection MISFETs in an extending direction thereof. The information storage capacitive element is similarly placed in the upper portion of the memory cell selection MISFET and is electrically connected to the other of the source and drain.
A DRAM described in Japanese Patent Application Laid-Open No. Hei 7-7084 has been devised to provide a lower electrode (storage electrode) of each capacitor in a cylindrical form having an opening defined thereabove thereby to increase its surface area. Further, a capacitive insulating film is formed on the lower electrode and an upper electrode (plate electrode) is formed over the capacitive insulating film.
In a capacitor having such a lower electrode of cylindrical shape, a steplike offset or difference in level corresponding to the height of the capacitor occurs between a memory cell array region and a region other than a peripheral circuit region or the like.
If such a steplike offset exists, it is then difficult to adjust the exposure focus upon patterning an interconnection layer formed after the formation of the capacitor. As a result, fine wiring patterns cannot be obtained. With developments in miniaturization of a semiconductor integrated circuit device, the storage capacitive value required per unit area has increased and, therefore, the height of the capacitor has further increased. On the other hand, allowable margin values for adjustment of the exposure focus become increasingly more strict due to the miniaturization of each wiring pattern.
Japanese Patent Application Laid-Open No. Hei 4-10651 (corresponding U.S. Pat. No. 5,218,219) discloses a DRAM wherein in order to reduce the steplike offset between the aforementioned memory cell array region and peripheral circuit region, grooves are defined in an insulating film and capacitors are formed along inner walls of the grooves.